Step-by-Step Guide: Converting Verilog to VHDL with Open-Source ToolsConverting Verilog to VHDL can be necessary when moving between toolchains, integrating third-party IP, or maintaining legacy projects. This guide walks through a practical, reproducible workflow using open-source tools, covering considerations, tool selection, step-by-step conversion, verification, and troubleshooting. Examples use small code snippets to illustrate common issues and fixes.
Why convert Verilog to VHDL?
- Different teams or toolchains may prefer one HDL over the other.
- Some FPGA or ASIC flows and IP libraries require VHDL.
- VHDL has strong typing and explicitness that can aid maintainability and formal verification.
- Reusing existing Verilog IP can save time if conversion is reliable.
Tools you’ll need (open-source)
- iverilog — Verilog simulator and linting aid (for testing original Verilog).
- Yosys — Open-source synthesis framework with Verilog front-end and intermediate RTLIL.
- ghdl — VHDL simulator and analyzer.
- sv2v — Converts SystemVerilog to Verilog (helpful if Verilog uses SystemVerilog features).
- vhdl conversion helpers / custom scripts — Yosys can emit RTLIL which can be translated to VHDL via dedicated backends or scripts (e.g., yrtl2vhdl, myhdl or custom Python scripts). Some community tools: vhdlgen, yosys-plugin-vhdl, or third-party converters on GitHub.
- GNU Make / Python / shell for automation.
Install on Linux (Ubuntu example):
sudo apt update sudo apt install iverilog ghdl python3-pip git # Install Yosys (recommended from package or build from source) sudo apt install yosys # Install sv2v if needed git clone https://github.com/zachjs/sv2v.git cd sv2v cabal v2-install Notes:
- Exact package names and availability may differ by distribution. Build from source if needed.
- Some conversion helpers are community projects; evaluate their maturity before relying on them.
High-level conversion approaches
- Direct automated conversion (tool-based) — fastest, but may require manual fixes for unsupported constructs.
- Convert to an intermediate representation (IR) and generate VHDL — more control and typically more reliable for synthesisable code. Yosys’s RTLIL is a common IR.
- Manual rewriting — safest for complex or behavioral code, but labor-intensive.
For most practical cases, an IR-based automated approach with manual review hits the sweet spot.
Step 1 — Prepare and analyze the Verilog source
- Collect all source files and dependencies (modules,
defines, parameter files). - Lint and simulate the Verilog to ensure a known-good baseline.
- Lint with iverilog or third-party linters.
- Run unit tests or behavioral simulations.
Example:
iverilog -o tb_sim top.v module1.v module2.v testbench.v vvp tb_sim Fix any warnings/errors before conversion.
Step 2 — Normalize SystemVerilog/Verilog extensions
If your Verilog uses SystemVerilog constructs, convert them to pure Verilog where possible using sv2v:
sv2v src/sys_module.sv > src/sys_module.v For constructs that sv2v can’t convert automatically (UVM, complex assertions), plan for manual rewriting.
Step 3 — Synthesis/RTL extraction with Yosys
Yosys can read Verilog, perform synthesis passes, and produce RTLIL, which many downstream tools can use to generate VHDL.
Example Yosys script (convert.ys):
read_verilog src/*.v hierarchy -check -top top proc; flatten; opt show -format png -prefix rtl write_rtlil design.il Run:
yosys -s convert.ys This yields RTLIL and a synthesized netlist representation suitable for conversion to VHDL. Keep in mind:
- Synthesis normalizes constructs (e.g., transforms always blocks into registers/comb logic).
- Behavioral constructs not supported by synthesis (like delays, event controls) may be ignored or cause errors — address these first.
Step 4 — Convert RTLIL/netlist to VHDL
Options:
- Use a Yosys backend or plugin that writes VHDL (some forks/plugins add VHDL backend). Example command (if your Yosys supports it):
write_vhdl -noattr -std 2008 design.vhd - Use an intermediate netlist (EDIF, BLIF) and then a converter to VHDL.
- Use community tools (yrtl2vhdl, yosys-plugin-vhdl) or write a custom generator targeting instantiations, signals, and processes.
If using Yosys with VHDL backend installed:
yosys -p "read_verilog src/*.v; hierarchy -top top; proc; opt; write_vhdl design.vhd" If no backend is available, export an HDL-agnostic format (like JSON via “write_json”) and feed into a custom Python script to emit VHDL.
Step 5 — Fix language-level issues & adapt coding styles
Automated conversion often yields correct structure but not idiomatic VHDL. Common adjustments:
- Convert
wire/regsemantics to VHDL signals and processes. Use explicit types: std_logic, std_logic_vector, unsigned/signed where arithmetic is used. - Replace Verilog
assignwith concurrent signal assignments or processes. - Translate parameters to VHDL generics.
- Replace preprocessor `
definemacros with VHDL constants or generate statements. - Handle vector indexing differences and bit-order conventions carefully.
Example mapping:
- Verilog: reg [7:0] counter;
- VHDL: signal counter : std_logic_vector(7 downto 0);
Arithmetic example:
- Use ieee.numeric_std and cast vectors to unsigned/signed for arithmetic: “`vhdl library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;
signal a, b : std_logic_vector(7 downto 0); signal sum : std_logic_vector(7 downto 0);
sum <= std_logic_vector(unsigned(a) + unsigned(b));
--- ## Step 6 — Create a VHDL testbench and simulate with GHDL Convert or rewrite the testbench in VHDL. If you have an existing Verilog testbench, you can either: - Recreate tests in VHDL, or - Use mixed-language simulation (some simulators support Verilog + VHDL co-simulation; GHDL can co-simulate with certain tools, but mixed-language support is limited compared to commercial simulators). Basic GHDL workflow: ```bash ghdl -a design_pkg.vhd design.vhd tb.vhd ghdl -e tb ghdl -r tb --vcd=wave.vcd Open waveform in GTKWave:
gtkwave wave.vcd Step 7 — Functional verification and equivalence checking
- Run testbenches and stimulus to validate functional equivalence.
- Use formal or equivalence checkers where possible:
- Formal equivalence tools (commercial and some open-source projects) compare gate-level or RTL-level equivalence between original Verilog and generated VHDL netlist.
- Yosys can be used to synthesize both sides to RTLIL and compare using techniques like combinational equivalence checking (CEC) with tools like abc or custom scripts.
Simple approach:
- Simulate same test vectors on Verilog (iverilog/vvp) and VHDL (ghdl) and compare outputs (VCD traces or CSV logs).
Step 8 — Synthesis for target FPGA/ASIC
After functional verification:
- Synthesize the VHDL with your target vendor tools (Xilinx Vivado accepts VHDL; Intel Quartus too).
- Watch for vendor-specific attributes or pragmas that may need adapting.
- Ensure constraints (timing, pin assignments) are preserved or recreated.
Common pitfalls and fixes
- SystemVerilog-only constructs: replace or simplify before conversion.
- Blocking vs non-blocking assignment semantics: verify sequential logic carefully — synthesis may mask behavioral differences but simulation will reveal mismatches.
- Mixed-endian bit indexing: ensure consistent MSB/LSB convention.
initialblocks and simulation-only constructs: reimplement as reset behavior in VHDL or testbench code.- Macros and
ifdefguards: expand or convert to VHDL generate/generic mechanisms.
Example: Small conversion walkthrough
Verilog (counter.v):
module counter #(parameter WIDTH = 8)( input clk, reset, output reg [WIDTH-1:0] cnt ); always @(posedge clk or posedge reset) begin if (reset) cnt <= 0; else cnt <= cnt + 1; end endmodule VHDL equivalent:
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter is generic ( WIDTH : integer := 8 ); port ( clk : in std_logic; reset : in std_logic; cnt : out std_logic_vector(WIDTH-1 downto 0) ); end entity; architecture rtl of counter is signal cnt_r : unsigned(WIDTH-1 downto 0); begin cnt <= std_logic_vector(cnt_r); process(clk, reset) begin if reset = '1' then cnt_r <= (others => '0'); elsif rising_edge(clk) then cnt_r <= cnt_r + 1; end if; end process; end architecture; Automation tips
- Write a Makefile or Python script to run conversion steps: normalize, synthesize with Yosys, export, convert, simulate.
- Keep a mapping document of module names, parameters, and signal types.
- Use unit tests with fixed vectors to quickly detect regressions.
When to prefer manual rewriting
- Highly behavioral code (delays, real-time models, analog-like constructs).
- Code using vendor-specific simulation features or third-party verification libraries.
- When readability and maintainability of VHDL are priorities over speed of conversion.
Summary checklist
- [ ] Lint and simulate original Verilog.
- [ ] Convert SystemVerilog extensions.
- [ ] Synthesize/extract RTL with Yosys.
- [ ] Convert RTLIL/netlist to VHDL (Yosys backend or custom script).
- [ ] Adjust types, generics, and idioms to VHDL.
- [ ] Recreate or port testbenches; simulate with GHDL.
- [ ] Equivalence check and fix semantic mismatches.
- [ ] Synthesize in target vendor tool and validate constraints.
If you want, I can:
- Provide a ready-to-run Yosys script and Python converter scaffold for a small project.
- Convert a sample Verilog file you paste here into VHDL and explain each change.
Leave a Reply